1. Field of the Invention
The present invention relates to a static semiconductor memory device, and particularly a structure for rapidly and accurately reading out data. More particularly, the invention relates to a structure for reducing interference between bit lines upon reading out of memory cell data in a semiconductor memory device.
2. Description of the Background Art
FIG. 17 schematically shows a whole structure of a conventional static semiconductor memory device. In FIG. 17, the semiconductor memory device includes a memory cell array MA having memory cells arranged in rows and columns. FIG. 17 shows, by way of example, memory cells M1-M8 arranged in two rows and four columns. Word lines WL are arranged corresponding to the memory cell rows, respectively, and bit line pairs are arranged corresponding to the memory cell columns, respectively. In FIG. 17 there are shown, as a representative, a word line WL1 arranged corresponding to the row of memory cells M1-M4 and a word line WL2 arranged corresponding to the row of memory cells M5-M8. As for the bit line pairs, there are shown bit lines B1 and /B1-B4 and /B4 in FIG. 17.
The semiconductor memory device further includes: a bit line precharge circuit 11 for precharging these bit lines B1 and /B1 to B4 and /B4 to a power supply voltage level in response to a clock signal T; a row decode circuit 14 operating in synchronization with clock signal T and decoding a row address signal X applied thereto to drive a word line corresponding to the addressed row to the selected state; a column decode circuit 5 for decoding column address signals Y0 and Y1 applied thereto to drive one of column select signals DY1-DY4 selecting an addressed column to the selected state; a read/write circuit 6 operating in synchronization with clock signal T and reading and writing data in accordance with a write signal WE; and a multiplexer 2 for coupling a bit line pair corresponding to the selected column to read/write circuit 6 via internal data lines DL and /DL in accordance with column select signals DY1-DY4 received from column decode circuit 5.
Multiplexer 2 includes column select gates CG arranged corresponding to the respective memory cell columns. In FIG. 17, there are shown column select gates CG1-CG4 arranged corresponding to bit lines B1 and /B1 to B4 and /B4 in four columns, and made conductive when corresponding column select signals DY1-DY4 are active, respectively.
Bit line precharge circuit 11 includes bit line load circuits L1-L4 arranged corresponding to bit line pairs B1 and /B1 to B4 and /B4, respectively. Each of bit line load circuits L1-L4 includes a P-channel MOS transistor P1 for precharging a corresponding bit line B (B1-B4) to the power supply voltage level when turned on, and a P-channel MOS transistor P2 for precharging a complementary bit line /B (/B1-/B4) to the power supply voltage level when turned on.
Each of column select gates CG1-CG4 included in multiplexer 2 includes N-channel MOS transistors NI and N2, which are turned on, when corresponding column select signal DYi (i=1-4) is selected, to connect corresponding bit lines B and /B to internal data lines DL and /DL, respectively.
The static semiconductor memory device shown in FIG. 17 is a clock synchronous semiconductor memory device, which performs selection of a row and a column as well as write/read of data in synchronization with clock signal T. When clock signal T is at L level, all bit line load circuits L1-L4 are activated in bit line precharge circuit 11, and bit lines B1 and /B1 to B4 and /B4 are precharged to power supply voltage VCC level by corresponding P-channel MOS transistors P1 and P2. Row decode circuit 14 and column decode circuit 5 are inactive, and word lines WL1 and WL2 as well as column select signal DYi are in the unselected state.
When clock signal T attains H level, the memory select operation and access operation are performed. More specifically, row decode circuit 14 is activated to decode a row address signal X, for driving a word line WL (WL1 or WL2) corresponding to the addressed row to the selected state. At the same time, column address signals Y0 and Y1 are applied, and column decode circuit 5 is activated in synchronization with the rising of clock signal T to perform the decoding of the column address, for driving one of column select signals DY1-DY4 to the selected state in accordance with the result of decoding. Responsively, bit lines B and /B corresponding to the selected column are coupled to internal data lines DL and /DL, respectively.
In the data read operation, the voltages on bit lines B and /B precharged to the power supply voltage level, change in accordance with data stored in the selected memory cell, and a sense amplifier circuit included in read/write circuit 6 amplifies the voltage difference between the bit lines corresponding to this selected column to produce read data. In the data write operation, a write circuit included in read/write circuit 6 produces complementary internal write data in accordance with externally supplied write data, for transmission to bit lines B and /B corresponding to the selected column. In this data write operation, one of bit lines B and /B precharged to the power supply voltage level is driven to the ground voltage level in accordance with the internal write data.
In FIG. 18A, there is shown, by way of example, a structure of row decode circuit 14 shown in FIG. 17. In FIG. 18A, row decode circuit 14 includes an inverter circuit 14a for inverting row address signal X, an AND circuit 14b receiving an output signal of inverter circuit 14a and clock signal T, and transmitting a word line drive signal onto word line WL1, and an AND circuit 14c receiving clock signal T and row address signal X, and transmitting a word line drive signal onto word line WL2.
Row decode circuit 14 shown in FIG. 18A includes an AND type decode circuit as a unit decode circuit. Word lines WL2 and WL1 are selectively designated in accordance with H and L levels of row address signal X. A decode operation of row decode circuit 14 shown in FIG. 18A will now be briefly described with reference to a timing chart of FIG. 18B.
When clock signal T is at L level, the output signals of AND circuits 14b and 14c are at L level, and both word lines WL (WL1 and WL2) are at L level. In FIG. 18B, externally applied row address signal X applied, for example, from a processor changes in synchronization with the falling of clock signal T.
When clock signal T rises to H level, AND circuits 14b and 14c are enabled, and one of word lines WL1 and WL2 is driven to the selected state in accordance with row address signal X. When row address signal X is at H level, AND circuit 14c transmits the word line drive signal onto word line WL2, and word line WL2 is driven to the selected state. When row address signal X is at L level, AND circuit 14b activates the word line drive signal to drive word line WL1 to the selected state. When clock signal T falls to L level, both of the output signals of AND circuits 14b and 14c attain L level, and the memory cell access cycle ends. Accordingly, word lines WL1 and WL2 attain the unselected state, and bit line precharge circuit 11 shown in FIG. 17 precharges bit lines B and /B to the power supply voltage level.
FIG. 19 shows, by way of example, a structure of memory cells M1-M8 shown in FIG. 17. FIG. 19 shows memory cell M1 as a representative. These memory cells M1-M8 have the same structure.
In FIG. 19, memory cell M1 includes; a P-channel MOS (insulated gate type field effect) transistor TR1 which is connected between a power supply node and a storage node SNA, and has a gate connected to a storage node SNB; a P-channel MOS transistor TR2 which is connected between the power supply node and storage node SNB, and has a gate connected to storage node SNA; an N-channel MOS transistor TR3 which is connected between storage node SNA and the ground node, and has a gate connected to storage node SNB; an N-channel MOS transistor TR4 which is connected between storage node SNB and the ground node, and has a gate connected to storage node SNA; an N-channel MOS transistor TR5 which is turned on to connect storage node SNA to bit line B1 in response to the word line drive signal on word line WL1; and an N-channel MOS transistor TR6 which is turned on to connect storage node SNB to bit line /B1 in response to the word line drive signal on word line WL1. In memory cell M1 shown in FIG. 19, MOS transistors TR1 and TR3 form a CMOS inverter circuit, MOS transistors TR2 and TR4 form a CMOS inverter circuit, and these inverter circuits form a latch circuit. Thus, storage nodes SNA and SNB store data complementary to each other.
When word line WL1 is in the selected state, MOS transistors TR5 and TR6 are turned on to connect storage nodes SNA and SNB to bit lines B1 and /B1, respectively. Accordingly, one of bit lines B1 and /B1 precharged to the power supply voltage level is discharged in accordance with the data stored on storage nodes SNA and SNB, and the voltage level of the one bit line lowers.
In the operation of reading the memory cell data, bit line precharge circuit 11 shown in FIG. 17 is inactive so that bit lines B1 and /B1 are in the floating state, and the voltage level of one of bit lines B1 and /B1 lowers at a certain rate to a certain level. The voltage lowering rate and the attained voltage level are determined by the load capacitance of bit line B and /B and the current drive capability of MOS transistors TR3 and TR4. The voltage difference, appearing between bit lines B1 and /B1, is transmitted via the corresponding column select gate to read/write circuit 6, and is differentially amplified by the sense amplifier circuit included read/write circuit 6, so that the data is read out.
FIG. 20 schematically shows, by way of example, a structure of read/write circuit 6 shown in FIG. 17. In FIG. 20, read/write circuit 6 includes: an inverter circuit 6a which inverts write signal WE; an AND circuit 6b which receives clock signal T and an output signal of inverter circuit 6a, and produces a sense amplifier enable signal SAE; an AND circuit 6c which receives clock signal T and write signal WE, and produces write driver enable signal WDE; a sense amplifier 6d which is activated, when sense amplifier enable signal SAE is active, to differentially amplify the voltage difference appearing between internal data lines DL and /DL for producing external read data DQ; and a write driver 6e which is activated, when write driver enable signal WDE is active, to produce complementary internal write data from external data DQ for transmission onto internal data lines DL and /DL.
Sense amplifier 6d is formed of a differential amplifier circuit, and differentially amplifies a relatively small voltage difference appearing between internal data lines DL and /DL to produce the external read data. Write driver 6e has a relatively large current drive capability, and produces complementary internal write data in accordance with external data DQ to set the storage data of a selected memory cell to the logical level corresponding to the write data. Therefore, the current drive capability of write driver 6e is sufficiently larger than the latching capability of the latch circuit of memory cell M.
In the structure of read/write circuit 6 shown in FIG. 20, when clock signal T is at L level, both sense amplifier enable signal SAE and write driver enable signal WDE are at L level, and both sense amplifier 6d and write driver 6e are inactive. Thus, read/write of data is not performed. When clock signal T rises to H level, AND circuits 6b and 6c are enabled, and one of sense amplifier enable signal SAE and write driver enable signal WDE is activated in accordance with write signal WE. When write signal WE is at L level, sense amplifier enable signal SAE is activated, and responsively, sense amplifier 6d differentially amplifies the voltage difference between internal data lines DL and /DL. When write signal WE is at H level, write driver enable signal WDE is activated, and write driver 6e produces the internal write data in accordance with the external write data, for transmission onto internal data lines DL and /DL.
FIG. 21 is a signal waveform diagram representing a data read operation of sense amplifier 6d shown in FIG. 20. When clock signal T attains H level as shown in FIG. 21, row decode circuit 14 shown in FIG. 18A is activated to drive word line WL, arranged corresponding to the addressed row, to the selected state. In this state, bit line precharge circuit 11 shown in FIG. 17 is inactive and the voltage levels of bit lines BL and /BL change in accordance with the stored data of memory cell. In parallel with this word line selecting operation, column decode circuit 5 (see FIG. 17) performs the column select operation, and the voltage levels of the bit line pair corresponding to the selected column are transmitted onto internal data lines DL and /DL, and accordingly the voltage levels of internal data lines DL and /DL change. FIG. 21 represents the operation in the case where internal data lines DL and /DL are precharged to the power supply voltage level. Sense amplifier 6d amplifies the voltage difference between internal data lines DL and /DL to produce the external read data in accordance with activation of sense amplifier enable signal SAE.
Therefore, sense amplifier 6d differentially amplifies the minute voltage difference appearing on internal data lines DL and /DL so that fast reading of the data can be achieved. Data Q0 and Q1 externally read out are taken, e.g., by an external processor in synchronization with the falling of clock signal T, and the processing of the read data starts in the following cycle of clock signal T.
Since sense amplifier 6d amplifies the differential data, it is preferable for fast reading of the data to apply as large a voltage difference as possible to sense amplifier 6d in a short time.
FIG. 22 schematically shows a planar layout of active regions (impurity regions) of memory cells M1-M4 arranged in one row and four columns. In FIG. 22, U-shaped impurity regions (active regions) 20 are aligned in the row direction, and T-shaped impurity regions (active regions) 21 are aligned with U-shaped impurity regions 20, respectively in the column direction. U-shaped impurity region 20 is divided into left and right half impurity regions 20a and 20b. T-shaped impurity region 21 is divided into left and right half impurity regions 21a and 21b. 
One memory cell M (M1-M4) is formed of left half region 20a of U-shaped impurity region 20, right half region 20b of adjacent U-shaped impurity region 20 and impurity regions 21a and 21b facing to these impurity regions 20a and 20b, respectively, as depicted by broken lines in FIG. 22. U-shaped impurity region 20 is used for forming an accessing transistor and a driving transistor (i.e., discharging transistor in a latch circuit) of memory cell M. Thus, N-channel MOS transistors are formed in U-shaped active region 20. T-shaped active region 21 is used for forming a pull-up P-channel MOS transistor in the latch circuit of the memory cell M. Active regions 20 and 21 shown in FIG. 22 are arranged repetitively in the row direction, and are also arranged repetitively in the column direction with a mirror-inversion relationship.
FIG. 23 schematically shows a layout of interconnection lines for active regions 20 and 21 shown in FIG. 22. In FIG. 23, first metal interconnection lines (first-level metal interconnection lines) 24a-24f extending in the column direction in the memory cell regions are arranged corresponding to active regions 20a, 20b, 21a and 21b. First metal interconnection line 24a is electrically connected to active region 20b via a first contact (contact between the first metal interconnection line and the active region) 22a. First metal interconnection line 24b is electrically connected to active region 21b via first contact 22b. Polycrystalline silicon interconnection lines 23a extending in the column direction are arranged near first metal interconnection lines 24a and 24b. Polycrystalline silicon interconnection line 23a forms gate electrodes of the transistors, which form a latch circuit in the memory cell.
A first metal interconnection line 24d is arranged near polycrystalline silicon interconnection line 23a. First metal interconnection line 24d is connected to active region 20b via a first contact 22c, and is also electrically connected to active region 21b via a first contact 22d. First metal interconnection line 24c is arranged in parallel with active region 20b and extending in the column direction. First metal interconnection line 24c is connected to active region 20b via a first contact 22f A polycrystalline silicon interconnection line 27 extending in the row direction is arranged near first contact 22f Polycrystalline silicon interconnection line 27 forms word line WL, extends in the row direction, and crosses U-shaped active regions 20 shown in FIG. 22 to form gates of the access transistors of the memory cells aligned in the row direction.
First metal interconnection lines 24e and 24f are arranged extending in the column direction and adjacent to first metal interconnection lines 24c and 24d, respectively, in the memory cell region. First metal interconnection line 24e is electrically connected via a first contact 22g to underlying active region 20a. First metal interconnection line 24f is connected electrically via a first contact 22h to active region (impurity region) 20a formed beneath. Further, first metal interconnection line 24f is connected to active region 21a via a first contact 22i. A polycrystalline silicon interconnection line 23b is arranged extending in the column direction and adjacent to first metal interconnection line 24f in the memory region. Polycrystalline silicon interconnection line 23b is connected to first metal interconnection line 24d via a first contact 22e. Polycrystalline silicon interconnection line 23a is connected to first metal interconnection line 24f via a first contact 22e. First metal interconnection lines 24d and 24f form storage nodes of the memory cell.
First metal interconnection lines 24a and 24b are arranged corresponding to active regions 20 and 21, respectively, near polycrystalline silicon interconnection line 23b. First metal interconnection lines 24a and 24b are electrically connected to the corresponding active regions via first contacts, respectively. First metal interconnection lines 24a and 24b adjacent to polycrystalline silicon interconnection line 23b form power supply nodes of the memory cells.
In the interconnection line layout shown in FIG. 23, first metal interconnection line 24a forms a ground node for transmitting the ground voltage, and first metal interconnection line 24b forms a power supply node for transmitting the power supply voltage. Polycrystalline silicon interconnection lines 23a and 23b form transistor gates of MOS transistors forming the latch circuits in the memory cells. First metal interconnection lines 24c and 24e form leader interconnection lines for connecting the access transistors of the memory cells to the corresponding bit lines. First metal interconnection lines 24d and 24f form storage nodes for storing complementary data of the memory cells.
The interconnection lines for transmitting the power supply voltage and the ground voltage are arranged in a region between the memory cells. The first metal interconnection lines forming the power supply nodes and the storage nodes are arranged with substantially equal pitches in the row direction, and an intermediate interconnection lines for bit line connection in one memory cell are spaced from each other in the row direction by an extremely small distance. Thus, the memory cells are arranged in a high density.
The interconnection line layout shown in FIG. 23 is repeated in the row direction, and is repeated in the column direction in a mirror-inversion fashion.
FIG. 24 schematically shows a layout of second level metal interconnection lines arranged above the interconnection line layout shown in FIG. 23. In FIG. 24, second level metal interconnection lines (referred to simply as second interconnection line) 30a and 30b are arranged corresponding to first metal interconnection lines 24a and 24b, respectively. These second metal interconnection lines 30a and 30b are electrically connected to corresponding first metal interconnection lines 24a and 24b via second contacts 31a and 31b, respectively, although first metal interconnection line 24b is not shown in FIG. 24.
Second metal interconnection lines 32a and 32b are aligned to first metal interconnection lines 24c and 24e shown in FIG. 23, and are connected via second contacts 31c and 31d to corresponding first metal interconnection lines 24c and 24e arranged beneath, respectively. These second metal interconnection lines 32a and 32b form the bit lines, and are coupled to corresponding bit line load circuits.
FIG. 25 schematically shows a layout of third metal interconnection lines arranged above the interconnection line layout shown in FIG. 24. In FIG. 25, a third level metal interconnection line (referred to simply as third interconnection line) 37 is arranged crossing second metal interconnection lines 32a and 32b. A third metal interconnection line 35 is arranged parallel to third metal interconnection line 37 and extending in the row direction to cross second metal interconnection line 30a. Further, a third metal interconnection line 36 is arranged extending in the row direction to cross second metal interconnection line 30b. Third metal interconnection line 37 is electrically connected at a portion, not shown in the figure, to polycrystalline silicon interconnection line 27 forming word line WL shown in FIG. 23, and transmits a word line drive signal to the gates of the access transistors of a corresponding row at high speed.
Third metal interconnection line 35 is electrically connected to second metal interconnection line 30a via a third contact 34a, and third metal interconnection line 36 is electrically connected to second metal interconnection line 30b via a third contact 34b. Third metal interconnection line 35 transmits ground voltage GND, and third metal interconnection line 36 transmits power supply voltage VCC.
In the interconnection line layout shown in FIG. 25, each bit line pair is formed of second metal interconnection lines 32a and 32b, which form a pair and are located between adjacent two contact sets each including third contacts 34a and 34b aligned in the column direction. FIG. 25 shows bit lines B1 and /B1 to B4 and /B4. These bit lines are formed of the second metal interconnection lines, and are arranged in the same conductive layer. Therefore, a parasitic capacitance C1 or C2 is present between the second metal interconnection lines adjacent to each other with an interlayer insulating film interposed. These parasitic capacitances C1 and C2 act as follows.
For bit line pairs B2, /B2, B3 and /B3 shown in FIG. 26, it is now assumed that data at H level is read onto bit lines B2 and B3, and data at L level is read onto bit lines /B2 and /B3. In this state, bit lines B2 and B3 are already precharged to H level (power supply voltage level) by the bit line load circuit. In the operation of reading data at H level, the voltage levels of bit lines B2 and B3 do not change. Bit lines /B2 and /B3 are discharged toward the ground voltage level via the drive transistors (MOS transistors TR4 in FIG. 19) in the selected memory cells.
Parasitic capacitance C1 is present between bit lines B2 and /B2, parasitic capacitance C2 is present between bit lines /B2 and B3, and parasitic capacitance C1 is present between bit lines B3 and /B3.
When voltage levels of bit lines /B2 and /B3 change in the operation of reading memory cell data, this voltage change is therefore transmitted to bit line B3 via parasitic capacitances C1 and C2, and the voltage level of bit lines B3 to be held at H level lowers through the capacitive coupling, as shown in FIG. 27. When the voltage level of bit line B3 lowers, the pull-up transistor (MOS transistor TR1 in FIG. 19) of the memory cell may supply the current, but does not have a capability of compensating for the lowering of the voltage level of bit line B3. Therefore, this capacitance coupling acts to reduce a voltage difference xcex94V between bit lines B3 and /B3 in the operation of reading the memory cell data (i.e., the changing rate of the amplitude between the bit lines decreases). In the normal state, at a time ta, the sense margin for the sense amplifier is sufficiently large, and the sense operation is to be performed for reading the memory cell data at the time ta. In the case where the capacitive coupling is present, however, it is necessary to read the data by activating the sense amplifier at a time tb for producing voltage difference xcex94V of the same magnitude as that in the case where no capacitive coupling is present. Therefore, such a problem arises that the data cannot be read fast. If the sense amplifier is activated at a faster timing, the sense margin is insufficient, and erroneous data reading may result.
In particular, if the elements have miniaturized structures and the bit line pitch is accordingly made small, the value of capacitance between the bit lines becomes large to increase the influence by the interference between the bit lines, and accurate and fast reading of data may be impossible.
For reading the data as fast as possible, it is necessary to read the data via the sense amplifier while the voltage difference between the bit lines is small. If the voltage difference between the bit lines changes due to the interference between the bit lines caused by the above capacitive coupling, such a problem arises that the data cannot be read fast and accurately.
Japanese Patent Laying-Open No. 4-186671 discloses a structure for reducing noises between memory cells in a static semiconductor memory device. In this prior art, consideration is given to the ground voltage noises caused by the discharging current flowing to a ground line provided corresponding to each memory cell row when a memory cell is selected. However, no consideration is given to the decrease in the read voltage difference (voltage difference between the paired bit lines) due to the interference between the bit lines, and no countermeasures are taken against the inter-bit-line interference.
Further, a structure for reducing the inter-bit-line noises in a dynamic semiconductor memory device (DRAM) is disclosed in Japanese Patent Laying-Open No. 5-109287. This prior art reference discloses a structure, in which the bit lines have a so-called twist bit line structure for causing a common phase noises on paired bit lines. Although this prior art reference discloses a structure, in which paired bit lines are arranged sandwiching a bit line of another bit line pair, this structure is a so-called xe2x80x9cpseudo two intersection point memory cell structurexe2x80x9d, which complicates the layout for crossing the bit lines. Further, no consideration is given to the structure, in which the bit lines in a pair are connected to one memory cell, and the memory cell data are simultaneously read onto the paired bit lines. In this prior art reference, no consideration is given to a way of selecting a memory cell for reducing the inter-bit-line interference.
An object of the present invention is to provide a static semiconductor memory device, in which data can be read out fast and accurately while suppressing inter-bit-line interference.
Another object of the invention is to provide a static semiconductor memory device having a bit line layout, in which inter-bit-line interference can be easily suppressed.
A static semiconductor memory device according to the present invention includes a plurality of static memory cells arranged in rows and columns, and a plurality of word lines arranged, by a predetermined number, for each row of the memory cells. The memory cells aligned in the same row are connected to predetermined word lines among the predetermined number of word lines in a corresponding row.
The static semiconductor memory device according to the present invention further includes: a plurality of bit line pairs arranged corresponding to the columns of the memory cells, and are connected to the memory cells in the corresponding columns, respectively; and a bit line precharge/control circuit for maintaining the bit line arranged corresponding to the column adjacent to a selected column in a precharged state in accordance with a column address signal. The bit lines in each pair are arranged sandwiching a bit line of another bit line pair.
Upon selection of a memory cell, at least one of the adjacent columns is in the unselected state, and no selected memory cell data is read onto the adjacent one. Therefore, the memory cell data is not simultaneously read onto columns adjacent to each other, and change in read voltage of the memory cell data is not caused by the capacitive coupling via a parasitic capacitance between the bit lines. Therefore, it is possible to suppress inter-bit-line interference for the selected memory cell data, and it is possible to suppress reduction in voltage difference between the bit lines. Therefore, an inter-bit-line amplitude can be changed fast, and fast and accurate reading of data can be performed.
By maintaining the unselected bit line on the adjacent columns in the precharged state, this unselected bit line can be utilized as a shield layer, and the inter-bit-line interference can be reliably suppressed. In particular, the paired bit lines are arranged sandwiching the bit line of another bit line pair so that the inter-bit-line interference can be reliably suppressed in each bit line pair, and the accurate and fast reading of data can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.